Design-Reuse

MAZeT offers Interbus-IP for customized FPGA and ASIC implementation

Jena -- March 19 2009 - MAZeT GmbH offers IP cores for the Interbus protocol (SUPI4 / Phoenix Contact) for implementation in FPGAs and ASICs. The protocol chip for serial communication interfaces in ...
Design-Reuse

Alchip Unveils Industry's First Automotive ASIC Design Platform

November 22, 2023-- Alchip Technologies, Ltd. today rolled out the semiconductor industry's first Automotive ASIC platform at the Design Solutions Forum 2023. The platform targets the specialized ...
EDN

HDL-design challenges and philosophies for real-world ASIC implementations

New requirements for the MAC (medium-access control) and PHY (physical-layer interface) of a wireless-communications system can pose significant challenges for system designers looking to quickly get ...
EDN

FPGA-prototyping and ASIC-conversion considerations

The capacity and capability of modern FPGAs support the implementation of many digital systems, making FPGAs the platforms of choice for developing, prototyping, and deploying digital logic. Depending ...
Semiconductor Engineering

SpyGlass Application In An FPGA To ASIC Conversion Flow

Mapping from a field programmable gate array (FPGA) to an application specific IC (ASIC) is subject to some limitations. This white paper identifies some of the most common limitations in this mapping ...
Electronic Design

Structured ASICs

Heard about Structured ASICs but aren't sure exactly what they are and how to use them. In this edition of REFRESH! EEPN contributing editor, Andrew Leone, gives you a guided tour of these devices and ...